1. Field of the Invention
The present invention relates to a delay circuit, a semiconductor integrated circuit device containing a delay circuit and a delay method that enable signal propagation delay time to be adjusted in a semiconductor integrated circuit device without being affected by parasitic elements.
2. Description of the Related Art
Recent years have seen even further progress in the increasing speed of semiconductor integrated circuit devices. Due to the increased speed of the CPU and system LSI and the like, the operational leeway in the mutual transition timing between signals in the internal critical paths has become extremely short and the adjustment time steps and the adjustment accuracy of the delay circuit for the timing adjustment are becoming more and more exacting. Moreover, as a result of the increasing speed of the CPU and system LSI etc., there is also a need for a synchronous semiconductor memory device such as is typified by synchronous random access memory (referred to below as SDRAM) that operates at a high speed operating frequency of 200 MHz or more. In order to retain the phase lock as the speed of the external clock, which is a synchronized signal, increases, there is a need for a delay circuit capable of accurately adjusting the phase in extremely small time steps. Three related technologies are given below as responses to this requirement. Note that, for convenience, the number of delay steps in the descriptions below is given as four.
A delay circuit 1000 of the first related technology is shown in FIG. 8. The delay circuit 1000 shown in FIG. 8 is formed from a delay section 100 into which an input signal IN is input; selecting switch sections SW110, SW210, SW310, and SW410 for selecting one from among the four delayed output signals N10, N20, N30, and N40 each of which has a different amount of delay from the delay section 100; and an output buffer circuit 500 connected to the selecting switches SW110 through SW410 for outputting delayed signals as an output signal OUT.
The delay section 100 is formed from two stage inverter gates 101 and 102, 201 and 202, 301 and 302, and 401 and 402. The delay section 100 is structured such that a delayed output signal to which a sequential unit delay time is added at each two stage inverter gates (serving as a predetermined delay step for generating a unit delay time) is obtained. Namely, the output of the input signal IN after the two stage inverter gates 101 and 102 becomes the delayed output signal N10. Thereafter, the output from the two stage inverter gates 201 and 202 into which the delayed output signal N10 is input becomes the delayed output signal N20. The output from the two stage inverter gates 301 and 302 into which the delayed output signal N20 is input becomes the delayed output signal N30. Lastly, the output from the two stage inverter gates 401 and 402 into which the delayed output signal N30 is input becomes the delayed output signal N40. Thus four delayed output signals N10 through N40 comprising the sequentially added unit delay times are output. These delayed output signals N10 through N40 are input respectively into the selecting switch circuits SW110 through SW410. The selecting switch circuits SW110 through SW410 are provided with transfer gates for connecting the delayed output signals N10 to N40 to the output buffer circuit 500. The transfer gates are structured such that source terminals and drain terminals of PMOS and NMOS transistors are mutually connected together and drain terminals of PMOS and NMOS transistors are mutually connected together (T110 and T120, T210 and T220, T310 and T320, and T410 and T420). In addition, only the corresponding transfer gate is conducted to the gate terminal by selecting one from among the control signals /S(0,0), /S(1,0), /S(0,1), and /S(1,1) whose logic level is at a low level, and a predetermined delayed output signal (one from among N10 through N40) is connected to the output buffer circuit 500 and an output signal OUT having a predetermined delay time is output. Here, the NMOS transistor is conducted when a high level signal is input to the gate terminal, the output signals from the inverter gates INV110, INV210, INV310, and INV410 that invert the logic of the control signals /S(0,0) through /S(1,1) are input. The output buffer circuit 500 shapes the waveforms of the signals from the transfer gates and also ensures the performance of the driving of the output signal OUT that is input into an unillustrated later stage circuit. The output buffer circuit 500 is formed from two stage inverter gates 501 and 502, as is shown in FIG. 8.
Using this circuit structure, if the delay time of the signal propagation in the two stage inverter gates 101 and 102 through 401 and 402 is taken as the unit delay time, for the input signal IN, the delay circuit 1000 outputs as the output signal OUT a delayed signal that has this unit delay time as the delay step.
In a delay circuit 2000 of the second related technology shown in FIG. 9, instead of the selecting switch circuits SW110 through SW410 of the first delay circuit 1000 of the related technology, the selecting switch circuits SW120, SW220, SW320, and SW420 are provided. In the selecting switch circuits SW120 through SW420, a logic operation is performed on the delayed output signals N10 through N40 with the control signals /S(0,0) through /S(1,1) and they are then output to the output buffer circuit 503. Namely, the selecting switch circuits SW120 through SW420 output the logic operation result obtained when the delayed output signals N10 through N40 from the delay section 100 are input together with the control signals /S(0,0) through /S(1,1) into the NOR gates NOR 10, NOR210, NOR310, and NOR410. When a control signal /S(0,0) through /S(1,1) is selected and the level thereof becomes low, one of the inputs of the corresponding NOR gate NOR110 through NOR410 becomes low level and performs the inversion logic operation. The other control signals /S(0,0) through /S(1,1) become high level and each one of the inputs of the NOR gates NOR110 through NOR410 not selected becomes high level, and the outputs are fixed at low level. Only the output signal N11, N21, N31, or N41 of the selected selecting switch circuit SW120 through SW420 becomes the inverted signal of the delayed output signals N10 through N40 and the other output signals are fixed at low level. Accordingly, by performing a logic operation on the output signals N11 through N41 using the four input NOR gate 503, which is an output buffer circuit, they undergo a logic inversion and are output as the output signal OUT.
As a result of this circuit structure, if the delay time of the signal propagation in the two stage inverter gates 101 and 102 through 401 and 402 is taken as the unit delay time, for the input signal IN, the delay circuit 2000 outputs as the output signal OUT a delayed signal that has this unit delay time as the delay step.
A delay circuit 3000 of the third related technology shown in FIG. 10 is a circuit that is disclosed in, for example, FIG. 9 of Japanese Laid-Open Patent Publication No. 10-149227. This delay circuit 3000 differs from the delay circuit 1000 of the first related technology and the delay circuit 2000 of the second related technology in that it has a structure in which, after the input signal IN has been inverted by an inverter gate 800, it is split by selecting switch circuits SW130, SW230, SW330, and SW430 and input into the respective predetermined delay stages of the delay section 110. A predetermined delay signal is then output from the termination of the delay section 110 as the output signal OUT. Instead of the prior stage inverter gates 101, 201, 301, and 401 in the predetermined delay stage of the delay section 100, the predetermined delay stage of the delay section 110 is formed from NAND gates 103, 203, 303, and 403. The input into the NAND gate 103 at the head of the delay chain is connected to the output N12 from the selecting switch circuit SW130 and is also connected to the power supply voltage Vcc. In addition, each one of the inputs of each of the NAND gates 203, 303, and 403 is connected to the output from a predetermined delay stage from the previous stage, respectively, and the relevant output N22 through N42 from the relevant selecting switch circuit SW230 through SW430 is connected to the other input. When a signal from the control signals /S(0,0) through /S(1,1) inverted via inverter gates INV16 through INV46 becomes high level, one of the inputs of the corresponding NAND gate NAND110 through NAND410 becomes high level and performs the inversion logic operation. When the other control signals /S(0,0) through /S(1,1) become high level, each one of the inputs of the NAND gates NAND110 through NAND410 becomes low level and the outputs are fixed at high level. A signal that is in phase with the input signal IN is conveyed only to one of the output signals N12 through N42 of the selected selecting switch circuits SW130 through SW430 and the other output signals are fixed at high level. Because the input gates of the predetermined delay stages into which the signals N12 through N42 are input are also the NAND gates N103 through N403, one of the NAND gates 103 through 403 into which a high level is input actually performs the inversion logic operation. Because the power supply voltage Vcc is input into the NAND gate 103 at the head of the delay chain, a high level is output by each predetermined delay stage that receives a high level fixed signal from the non-selected selecting switch circuit continuing on from the head of the delay chain. The predetermined delay stage is composed of the NAND gate, that performs inversion processing on the high level input and the inverter gate. Accordingly, downstream from the predetermined delay stage that receives the signal from the selecting switch circuit that is selected and outputs a signal in-phase with the input signal, the unit delay time is sequentially added to this in-phase signal and is propagated.
As a result of this circuit structure, if the delay time of the signal propagation of the NAND gate and the inverter gate is taken as the unit delay time, for the input signal IN, the delay circuit 3000 outputs as the output signal OUT a delay signal that has this unit delay time as the delay step.
However, in the delay circuit 1000 of the first related technology, because the delay section 100 and the output buffer circuit 500 are connected via the transfer gates, ON resistances of the PMOS and NMOS transistors T110 and T120 through T410 and T420 forming the transfer gates are inserted into the signal path as parasitic resistance. This parasitic resistance has a small value if the size of the transistors forming the transfer gate is enlarged, however, in a semiconductor integrated circuit device, it is normal for the delay circuit 100 to have a multi stage structure because a substantial adjustable range span is necessary. For example, a DLL circuit used in SDRAM or the like is formed from 100 or more predetermined delay stages. In addition, because the area on a chip allocated to be taken up by the delay circuit 1000 is limited, it is not possible to make the size of the transistor sufficiently large. Therefore, it is quite common for this parasitic resistance to attain a comparatively large value and to attain a value of approximately 100 ohms. Moreover, the output terminals of all the selecting switch circuits SW110 through SW410 are all joined together as the terminal N100 and, in addition to the wiring capacitance and input gate capacitance of the output buffer circuit 500, the junction capacitance of the source and the drain of the PMOS and NMOS transistors T110 and T120 through T410 and T420 forming the transfer gates at the outputs of each of the selecting switch circuits SW110 through SW410 are also connected. Therefore, a large capacitance load is present as a parasitic capacitance at the terminal N100 and it is common for a parasitic capacitance of approximately 10 pF to be present depending on the number of predetermined delay stages. Accordingly, a parasitic CR time constant circuit is formed due to the load of the above parasitic resistance and parasitic capacitance in the signal path from the output of each predetermined delay stage of the delay section 100 to the output buffer circuit 500 so that not only is a signal propagation delay generated, but the signal waveform itself rounds. Moreover, because the parasitic resistance and capacitance vary widely due to inconsistencies in the manufacturing of the semiconductor integrated circuit devices, the delay amount and the like of these parasitic elements are also varied. If the time constant of this parasitic delay circuit is calculated from the above numerical example, it is approximately 1 nsec. Because this is a time that is approximately ten times the size of the unit delay time, a delay from the parasitic element of approximately ten times the adjustment value of the delay time is added to the adjustment value of the unit delay time causing the problem that it is not possible to accurately adjust the delay amount. In particular, as adjustment of the delay amount in more minute time step will henceforth be required in response to the ever increasing speed of semiconductor integrated circuit devices, it is going to be difficult to accurately perform the delay adjustment. Moreover, circuit operation is necessary in short pulses, however, the concern exists that the short pulses will become flattened and disappear due to the rounding of the waveform caused by the parasitic delay elements. In this case, the problem arises that the semiconductor integrated circuit device might cause operational malfunctions.
The rounding and the like of the signal waveform caused by the parasitic CR time constant circuit can be improved by increasing the drive capacity of the output inverter gates 102 through 402 of each of the predetermined delay stages of the delay section 100 driving the terminal N100 from the terminals N10 through N40, which is the signal path. However, the problem with this is that while the delay—rounding effect caused by the parasitic elements becomes greater the more stages there are in the delay section 100, the increase in the drive capacity of the inverter gates 102 through 402 becomes limited by the restrictions of the allowable surface area on the chip, creating the concern that it will become even more difficult to respond to the demands for adjustment of the delay amount in even more minute time step to go with the increased speeds of the semiconductor integrated circuit devices.
In the delay circuit 2000 of the second related technology, because the outputs from the selecting switch circuits SW120 through SW420 are from the NOR gates NOR110 through NOR410, terminals N11 through N41, which are individual signal paths, are connected to each of the selecting switch circuits SW120 through SW420. Therefore, in the delay circuit 2000 having a multi stage structure, because more of the terminals N11 through N41 are needed and a large area is required for the wiring on the chip surface, the problem arises that the further integration of the semiconductor integrated circuit device is held back. In addition, a predetermined logic circuit is also required as the output buffer circuit in order for a delay signal selected from these signals for the input signal IN to be output to the output terminal OUT. In FIG. 9, a four input NOR gate NOR503 is used as an example of an output buffer circuit for performing the logic operation on the four signals N11 through N41. However, because the dimensions of the logic circuit become more complex as the more terminals N11 through N41 are needed as signal paths in the multi stage structure delay circuit 2000 requiring a large area of the chip surface, the problem arises that the further integration of the semiconductor integrated circuit device is held back.
In a delay circuit 3000 of the third related technology, the output terminal N800 of the inverter gate 800 for inverting the input signal IN is connected all of the NAND gates NAND110 through NAND410 forming the selecting switch circuits SW130 through SW430. Because the number of the NAND gates that need to be connected to the output terminal N800 of the inverter gate 800 is proportional to the number of predetermined delay stages, the gate capacitance of the terminal N800 that needs to be driven by the inverter gate 800 increases as the structure of the delay circuit 3000 becomes more multi staged. Accordingly, the problem arises in the delay circuit 3000 having a multi stage structure that, as a result of the drive capacity of the inverter gate 800 becoming more and more insufficient as the capacitance load of the terminal N800 increases, the possibility exists that short pulse waveform will become ragged.
Moreover, in each predetermined delay stage in the delay section 110, while the latter stage gates are the inverter gates 102 through 402, the former stage gates are formed from the NAND gates 103 through 403. Here, because the structure of the transistors in each gate relating to the output terminal is a balanced symmetrical placement between the power supply voltage Vcc side and the ground potential Vss side in the case of the inverter gate, there is no difference between the drive capacity of the source and sink drives. However, in the case of the NAND gate, while the PMOS transistors are connected in parallel on the power supply voltage Vcc side, on the ground potential Vss side, the NMOS transistors are connected in series. Therefore, the drive capacity is unbalanced because the drive capacity of the sink drive is weaker than the drive capacity of the source drive. Namely, when a pulse waveform is applied to the input signal IN, the fall waveform becomes rounder compared with the rise waveform of the output of the NAND gate 103 through 403. This shows that a larger delay is generated corresponding to the rise waveform compared with the fall waveform of the input signal IN, and indicates that the propagated pulse width becomes narrower each time it passes through a predetermined delay stage. The problem is thus that the possibility exists that the short pulse propagation needed as the speed of the semiconductor integrated circuit device increases may not be obtainable.
Each of the above problems may be improved to a certain extent by increasing the drive capacity of the inverter gate 800 or by increasing the size of the NMOS transistors connected in series on the ground potential Vss side of the NAND gates 103 through 403. However, such measures create the problem that they require a large portion of the chip surface area thereby preventing further advances in the level of integration of the semiconductor integrated circuit device. In addition, any increase in the size of the transistor in itself means that there is an increase in the parasitic capacitance and gives rise to the problem that a greater number of stages in the structure of the delay circuit 3000 and faster operation are not able to be achieved.